Communications
Accelerating innovation for wireless and wired communications with efficient, scalable, and low power system IP
Overview
Overview
Wired and wireless communications are the backbone of our hyperconnected world. Critical development challenges include improving the speed, bandwidth, and reliability of networks while ensuring security and privacy. Reducing power consumption and increasing battery life for portable devices while maintaining high performance and functionality are top of mind for developers. In addition, the development of electronics for communication must balance cost-effectiveness and scalability with reliability and resilience, especially for the enablement of connectivity for critical applications such as medical devices, transportation, and defense.
Arteris’s network-on-chip (NoC) solutions are highly differentiated for wired and wireless communications by providing best-in-class configurability, scalability, and protocol support, achieving the lowest power consumption and cost while maintaining the best performance. The Magillem technology for hardware/software interface (HSI) development is especially suitable for wired communications designs with large sets of registers.

Advantages
Advantages
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Protocol Support
Arteris provides a wide range of network-on-chip (NoC) interconnect IP solutions that support multiple protocols, including AMBA, AXI, AHB, OCP, and ACE.
Optimized PPA
Arteris's interconnect IP solutions are designed to optimize the performance, power consumption, and cost of communications systems, which is critical for developing high-performance, feature-rich wired and wireless communications systems.
Advanced SoC Integration
Arteris's solutions aid developers of wired and wireless designs in addressing the challenges of integrating multiple heterogeneous processing elements, memory systems, and communication interfaces into a single SoC.
Arteris revolutionizes semiconductor design with
FlexGen - smart NoC IP
FlexGen’s built-in AI/ML-driven automation enables the generation of optimized NoC designs for complex SoCs, delivering expert-level results.
- 10x Productivity Boost
- Expert-Level Results
- Up to 30% Wire Length Reduction
Realize faster time-to-market, optimized power plus performance, and improved overall design economics with FlexGen.
Products
Products
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Customers
Trusted by innovative companies everywhere


Resources
Resources
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- Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design
- Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness
- Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications
- FlexGen Product Tour
- Cache Coherency in Heterogeneous Systems
- Integration Challenges for RISC-V Designs
- Promises and Pitfalls of SoC Restructuring
- Scaling Performance in AI Systems
- Arm & Arteris AI and ISO 26262 Presentation
- Arm TechCon: Implementing ISO 26262 Compliant AI Systems-on-Chip with Arm and Arteris
- Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)
- Building Better IP with RTL Architect NoC IP Physical Exploration
- Efficient Scaling of AI Accelerators Using NoC Tiling
- Implementing Low-Power AI SoCs Using NoC Interconnect Technology
- Implementing Machine Learning & Neural Network Chip Architectures
- ISO 26262: What to Expect From Your Chip or IP Provider
- Routing Congestion: The Growing Cost of Wires
- Safety Considerations for Network-on-Chip (NoC) Development
- The Role of Networks-on-Chips Enabling AI/ML Silicon and Systems
- Tiled Approach to System Scaling
- Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP
- Electronic Design: All About NoCs
- SemiWiki: A Broad View of Design Architectures and the Role of the NoC with Arteris’ Michal Siwinski
- EE Journal: The Freedom to Innovate: Arteris and the Rise of RISC-V
- EE Journal: The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster
- SemiWiki: The Impact of Using a Physically Aware NoC with Charlie Janac
- Re-Architecting SoCs for the AI Era
- Routing Congestion: The Growing Cost of Wires
- Scalability – A Looming Problem in Safety Analysis
- Security in Artificial Intelligence
- Using Machine Learning for Characterizations of NoC Components
- Using Virtual Prototypes to Improve the Traceability of Critical Embedded Systems Flow