Home » Products » FlexGen Smart Interconnect IP

FlexGen Smart Network-on-Chip (NoC) IP

AI-Enhanced Automation for Smarter SoC Design

FlexGen Smart NoC IP

Overview

Revolutionizing SoC Design with Intelligent
Automation

FlexGen^TM by Arteris redefines how SoC designers create Network-on-Chip IP by introducing cutting-edge AI heuristics and machine learning. This revolutionary IP automates NoC topology generation, achieving up to 10x faster design iterations than traditional methods.

With FlexGen, teams can optimize wire length, reduce latency, and improve power efficiency while minimizing manual intervention. Designed for automotive, data centers, and industrial electronics applications, FlexGen shortens design cycles, enabling faster time-to-market and/or multiple design explorations for the most complex systems.

Advantages

The Smarter Way to Build SoCs

Redefining productivity and efficiency in SoC design

10x Productivity Boost

Smart NoC generation is 10x faster than traditional NoC flows, shortening SoC or chiplet iterations from weeks to days for design efficiency.

Expert Level Results

3x improvement in engineering efficiency with expert quality of results with minimal effort across all NoCs. Algorithms minimize routing congestion, improving silicon area during physical design, with proven links to physical synthesis and place and route to support tapeout success.

Wire Length Reduction Driven Performance

Smart AI heuristics using machine-learning technology delivers an optimized topology with an average wire length reduction of up to 30%, reducing overall latency by up to 10%, plus power improvements across the design.

FlexGen Key Features

Smart NoC automation
Topology generation with minimum wire length
Scripting-driven regular topology creation
Incremental design capability
Auto-timing closure assist
… plus all the key features of FlexNoC 5

Explore additional features of FlexGen, download the datasheet.

Feature Spotlight

NoC Tiling — new feature with FlexGen

NoC tiling with mesh topology for NPUs, GPUs, TPUs with FlexGen. Up to 1024 tiles.

Scale performance
Condense design time
Speed testing
Reduce design risk

Create modular, scalable designs, enabling faster integration, verification and optimization.

Efficient Transport of Data Through the SoC

Arteris CodaCache® last-level cache:

Ideal for NoC applications with data re-use
Improves overall SoC latency and power

Efficient Transport of Data Through the SoC

NoC Integration Automated Flow

Automated flow to leverage SoC connectivity information:

Improved productivity with reduced process
Better quality with early errors detections thanks to the checkers

NoC Integration Automated Flow

FlexGen Product Benefits

Expert Level Output Quality

Generated smart NoC architecture and physical constraints

Significant Reductions in Wire Length

Minimizes die area, power consumption, and latency

10x Productivity Improvement

Reducing setup and configuration time from days to hours or minutes by automating repetitive, time-intensive tasks

Higher Frequencies, Lower Latencies

Using built-in NoC performance analysis exploration tools

Speedy Timing Closure

Early physical awareness for faster convergence without re-designs

Automated Verification

Saving hundreds of hours of work versus manual verification test benches

Higher Profit

Reduced TTM from FlexGen design efficiency savings

FlexGen Product Options

Seamlessly integrated extensions to the base FlexGen feature set

Option

Large Systems: XL and 2XL

NIU tiling
Mesh topology editor
Up to 2048 bits data bus
Virtual channel links
Write broadcast stations

learn more about option

Option

Resilience: Safety

ISO 26262 Functional Safety (FuSa)
Multi-ASIL support
Interconnect-wide ECC support

learn more about option

Option

Performance: Reorder Buffer

Single and Multi-channel reorder buffers (ROB):

Avoid ordering rule blocks
Avoid response serialization bottlenecks
Allow concurrent memory channel reads

learn more about option

Featured Solution

Arteris accelerates AI-driven silicon innovation with its expanded multi-die solution

Foundational technology for rapid chiplet-based design.

Flexible design scalability
Differentiated AI performance
Aligned with evolving industry standards

Built on silicon-proven NoC IP and Magillem™ automation to scale modular architectures, simplify multi-die projects, and compress development schedules.

Customer Testimonials

Trusted by innovative
companies everywhere

High-performance computing and AI SoCs have become very complex, creating expanding requirements to meet the energy efficiency targets and project schedules. Given our experience of working closely with Arteris in the past, we are excited about the smart NoC FlexGen technology and its ability to support our next-generation product innovation.

AMD is driving innovations that scale AI from cloud to client by continually developing leadership computing technologies and best-in-class IP. Integrating Arteris’ FlexGen NoC IP technology into a range of AMD chiplets, we can automate interconnect configuration and enable seamless connectivity among SoC components while strengthening the best end-to-end AI compute portfolio in the industry.

FlexGen’s AI-based automation has streamlined our design processes, delivering shorter wire lengths and lower latencies.