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Magillem Packaging

Captures Your IP Repository in a Pivot IEEE Format

Magillem Packaging

Overview

Scalable and Fully Automated Solution for Comprehensive Packaging

Using a data model based on the IP-XACT industry standard, Magillem Packaging handles all aspects of system integration for connectivity, configurability, and system memory map. It enables true IP reuse methodology with an interoperable design flow for complex SoCs, including register management, IP capture, and SoC IP assembly.

Magillem Packaging provides a nonintrusive, scalable, and automatic process for legacy and new IPs, enabling seamless packaging of the IP client portfolio. It brings both data accuracy and flexibility as it allows incremental or full packaging with IP-XACT compliance and data consistency that are ensured by construction and assessed with a built-in Magillem IP-XACT checkers suite.

Advantages

Comprehensive IP, Subsystem and Chiplet Packaging in a Reusable Format

Including configuration, implementation and verification for incremental and full packaging with a proven methodology

Correct by Construction IP-XACT Description

Improved quality without requiring any prerequisite IP-XACT expertise

True IP Reuse Methodology

For IPs and subsystems with vendor-independent IP packaging (IP-XACT based)

Single Source of Truth Environment for System Design

Enabling multi-purpose usage, ensuring data consistency

Magillem Packaging Key Features

IP-XACT 2022 support
HDL import: Verilog, SystemVerilog
Static elaboration support (with resolved configurations)
FileSet elaboration with full source file documentation
Bus interface automatic mapping of physical ports
Memory map intent capture
Catalog management
IP-XACT compliance checkers suite

Explore additional features of Magillem Packaging, download the datasheet.

Magillem Platform

Arteris SoC Integration Automation with the Magillem Platform

Learn about the powerful combination with Magillem Connectivity and Magillem Registers.

Category	Features	Magillem Packaging	Magillem Connectivity	Magillem Registers
IP-XACT Conversion	2009 to 2022
IP-XACT Conversion	2014 to 2022
Resource Management	Projects
	Catalogs
	Components
TGI	TGI API
HDL Import	Verilog support
	SystemVerilog support
	View & FileSet elaboration
Bus Interface	Auto mapping
Rules Checkers	Design and component
	Memory and system map
	Configurable checker severity
	Checkers waivers and contextual help
Assembly	Rule-based connectivity
	Bus/signal split/tie/open
	Hierarchical connection
	Glue logic insertion
	Feedthrough
RTL Netlist Generation	Verilog and SystemVerilog support
	Configurable header
	Keep parameter expressions
	Deep netlist
	Signals/netname management
	Automatic tie of unconnected inputs
Hierarchical Manipulations	Merge, Flatten, Move operations
	Virtual hierarchy
	Component stubbing operation
	Hierarchical parameter propagation
	Design statistic reporting
IP Update	Interface/port/parameter renaming/resizing/deletion/merging
	User mapping rules definition
	Automatic tie connection generation on new ports
	Automated correct-by-construction IP-XACT platform update at any level of hierarchy
	Component instance view update
Diff and Merge	List concurrent conflicts/changes
	Accept/Reject any change
	Conflict resolution wizard (choice selection, instance renaming…)
	On-the-fly checks to verify the validity of choices/conflict resolution
Import Memory Map Description	CSRSpec support
	SystemRDL support
	IP-XACT support
	Excel spreadsheets support
Generate HSI Outputs	RTL register bank (VHDL, Verilog, SystemVerilog)
	Customized C Header files
	UVM RAL files
	Documentation (Word, FrameMaker, HTML)
	SystemRDL description
	IP-XACT description
	Excel spreadsheet

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