Magillem
Connectivity
Accelerate the Design of Complex Systems With a Complete SoC Integration Solution
Overview
Automate SoC Assembly to Eliminate Tedious Tasks and Focus on What Matters Most
For design teams coping with exploding complexity, the Magillem® 5 Connectivity product streamlines and shortens by 30% the integration process to create correct by construction platforms.
It accelerates IPs deployment with continuous integration for an automated hardware development flow adapting to changes.
Reduce the Integration Process From Months to Weeks for Large-Scale SoC Designs
With a proven data model based on IP-XACT industry standard, Magillem Connectivity enables:
- IP packaging for efficient handling of all aspects of system integration for connectivity and configurability
- Automatic IPs instantiation and error-free connection process with solid API to access all the design data
- Comprehensive HSI automation ensures better quality design and faster productivity
The tool allows a significant jump in productivity, predictability with progress reporting, and portability of the design environment. For very large designs with thousands of instances, Magillem 5 Connectivity streamlines the integration process decreasing design cycle time by up to 30%.
Restructure for an Error-Free Design to Meet Power and Floorplanning Constraints
Restructure for an Error-Free Design to Meet Power and Floorplanning Constraints
Eliminate painful, manual steps across the build flow and optimize time-consuming netlist for physical design with Magillem Connectivity. It delivers automated hierarchy manipulation capabilities with built-in checks ensuring high-quality generated design.
- Separate RTL hierarchy and physical hierarchy, enabling powerful features including feedthrough connections for abutted floorplan and hard macros replication.
- Rapid response to physical design requirements, reducing the process from weeks to 1-2 days.
- Drastic improvement in development time and SoC quality through continuous integration flow.
Error-Free System Map Generation
Synchronizing connectivity and memory map information with full integration of Magillem Registers and Magillem Connectivity:
- Calculate and display the system map from the selected initiator.
- Confirm that memory regions defined in the memory map can be reached (presence of a physical path).
- Check that all the SW visible elements (registers or memory regions) in connected targets are present in the memory map.
Error-Free System Map Generation
Magillem Connectivity Key Features
- Project Management: Design navigation and data aggregation
- Parameters Configuration: Hierarchical propagation or overriding
- SoC Assembly: Bus i/f detection, rule-based connectivity, bus/signal split/tie/open, hierarchical connection, glue logic insertion, feedthrough
- Hierarchy Manipulations: Move, merge, and flatten a physical/virtual hierarchy for RTL restructuring/partitioning
- Platform Derivatives: With the incremental design, automatic update, and design diff and merge capability
- Comprehensive Checkers: Catch errors as you enter the design information before running any simulation
- Advanced Generation Capability: RTL Netlist generation, in addition to makefile scripts for an extensive range of EDA tools
- Tool Integration: Tight link with the connectivity tool to generate a system address map when both tools are combined
Explore additional features of Magillem Connectivity, download the datasheet.
NoC Integration Automated Flow
Automated flow to leverage SoC connectivity information:
- Improved productivity with reduced process
- Better quality with early errors detections thanks to the checkers
NoC Integration Automated Flow
Magillem Connectivity Product Benefits
True IP Reuse Methodology
For IPs and subsystems with vendor-independent IP packaging (IP-XACT based)
Shorten and Streamline the Integration Process
Accelerating the connectivity through automation
Continuous Integration
With a robust SoC build process that adapts safely and quickly to changes
Single Source of Truth
Enabling consistency and interoperability between the design flow steps
Correct by Construction
Thanks to the built-in checkers for higher quality designs
Reduce Effort and Rework
Automation ensures repeatability and eliminates human errors
Leverage Technical Expertise
Reduce tedious and time-consuming tasks to focus on core business
Boost Productivity
Higher quality design and shorter time to market
Arteris SoC Integration Automation with the Magillem Platform
Learn about the powerful combination with Magillem Packaging and Magillem Registers.
| Category | Features | Magillem Packaging | Magillem Connectivity | Magillem Registers |
|---|---|---|---|---|
| IP-XACT Conversion | 2009 to 2022 | |||
| 2014 to 2022 | ||||
| Resource Management | Projects | |||
| Catalogs | ||||
| Components | ||||
| TGI | TGI API | |||
| HDL Import | Verilog/SystemVerilog support | |||
| View & FileSet elaboration | ||||
| Bus Interface | Auto mapping | |||
| Rules Checkers | Design and component | |||
| Memory and system map | ||||
| Configurable checker severity | ||||
| Assembly | Rule-based connectivity | |||
| Bus/signal split/tie/open/feedthrough | ||||
| Glue logic insertion | ||||
| RTL Netlist Generation | Configurable header | |||
| Keep parameter expressions | ||||
| Signals/netname/tie management | ||||
| Hierarchical Manipulations | Merge, Flatten, Move operations | |||
| Parameter propagation | ||||
| IP Update | Rename/resize/delete/merge | |||
| User mapping rules definition | ||||
| Diff and Merge | Accept/Reject any change | |||
| Conflict resolution wizard | ||||
| Import Memory Map Description | SystemRDL support | |||
| IP-XACT support | ||||
| Excel spreadsheets support | ||||
| Generate HSI Outputs | RTL register bank (VHDL, Verilog, SystemVerilog) | |||
| Customized C Header files | ||||
| UVM RAL files | ||||
| Documentation (Word, FrameMaker, HTML) | ||||
| SystemRDL description | ||||
| IP-XACT description |
Product Options
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- Produce UPF script file
- Produce diagram based on domain hierarchies
- Powerful checks detecting early any issue or inconsistency between RTL and power intent
Resources
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