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Arteris provides network-on-chip (NoC) interconnect IP and System Integration Automation tools to improve performance, power consumption and die size of system-on-chip (SoC) devices for consumer electronics, mobile, automotive and other applications. Over 3 billion devices have been shipped to date containing Arteris IP.

Coherent Interconnect

Ncore IP tackles multicore SoC challenges through heterogeneous coherency, efficient caching, and high throughput for reliable, high-performance SoCs.

Coherent Interconnect

Ncore Cache Coherent Interconnect IP

Efficient coherent NoC interconnect that addresses key challenges in multi-core ASIC designs ensuring reliability, ISO26262 support, and optimized performance.

Non-Coherent Interconnect

Essential for efficient NoC designs, our high-end Flex family of products bring physical awareness to accelerate timing closure, reduce wires and increase SoC performance.

Non-Coherent Interconnect IP

FlexGen Smart Interconnect IP

Smart NoC IP automates the creation of high-performance NoC designs for 10x productivity boost, up to 30% wirelength reduction lowering latency and power consumption.

Non-Coherent Interconnect IP

FlexNoC Interconnect IP

Physically aware NoC with ISO26262 support option delivering up to 5X shorter turn-around-time on timing closure versus manual physical iterations.

Non-Coherent Interconnect IP

FlexWay Interconnect IP

Particularly well suited to cost-efficient, low-power Internet-of-Things (IoT) edge devices and microcontrollers (MCUs), also available with ISO26262 support.

Category	Features	FlexNoC	FlexGen
Target Audience and Scale	Smaller-scale MCU SoCs
	Small-medium scale SoCs
	Large scale SoCs
Instances Per Design	Single NoC instance
Instances Per Design	Multiple NoC instances
Network Interface Units (NIUs)	Up to 50 NIUs
	Up to 200 NIUs
	Up to 1000 NIUs	with XL option	with XL option
Compatibility	AXI, AHB, APB, OCP, PIF, AMBA5
Compatibility	ACE-Lite
Smart NoC Automation	Topology generation with minimum wire length
	Scripting-driven regular topology creation
	Incremental design capability
Physical Awareness	Automatic timing closure assistance
Physical Awareness	Floorplan visualization
Advanced Scalability	NIU tiling	with XL option	with XL option
	Mesh topology editor	with XL option	with XL option
	Write broadcast stations	with XL option	with XL option
	Virtual channel links	with XL option	with XL option
	Source synchronous asynchronous bridges	with XL option	with XL option
	Up to 1024 bits data bus	with XL option	with XL option
	512 pending transaction support	with XL option	with XL option
Optimizations	Optimization for performance, area and wire length
	Advanced Quality of Service (QoS)
	Power management and security
	Address and data protection schemes
	Advanced in-circuit debug features
	Multi-cycle SRAM support
	Floorplan visualization
Add-on Options	Memory Re-order Buffer option
	Reliability option
	Safety (up to ISO 26262 ASIL D) option
	Advanced Scalability (XL) option
Markets	Automotive, Communications, Consumer Electronics, Enterprise Computing and Industrial Markets

Last-Level Cache

CodaCache IP optimizes SoC performance by minimizing memory latency. This highly configurable shared cache improves data flow and power efficiency.

Last-Level Cache

CodaCache Last-Level Cache IP

A last-level cache IP that solves key SoC challenges like performance, data access, timing closure, and layout congestion with a configurable caching solution.

Packaging

Package any IP into an IP-XACT file, enabling documentation using XML meta-data for multiple purpose usage, facilitating the integration, configuration, and validation of the IP.

Packaging

Magillem Packaging

A fully automated solution to import legacy RTL and create correct by-construction IP-XACT description, map the physical ports into bus interface, and capture the memory map.

Category	Features	Magillem Packaging	Magillem Connectivity	Magillem Registers
IP-XACT Conversion	2009 to 2022
IP-XACT Conversion	2014 to 2022
Resource Management	Projects
	Catalogs
	Components
TGI	TGI API
HDL Import	Verilog support
	SystemVerilog support
	View & FileSet elaboration
Bus Interface	Auto mapping
Rules Checkers	Design and component
	Memory and system map
	Configurable checker severity
	Checkers waivers and contextual help
Assembly	Rule-based connectivity
	Bus/signal split/tie/open
	Hierarchical connection
	Glue logic insertion
	Feedthrough
RTL Netlist Generation	Verilog and SystemVerilog support
	Configurable header
	Keep parameter expressions
	Deep netlist
	Signals/netname management
	Automatic tie of unconnected inputs
Hierarchical Manipulations	Merge, Flatten, Move operations
	Virtual hierarchy
	Component stubbing operation
	Hierarchical parameter propagation
	Design statistic reporting
IP Update	Interface/port/parameter renaming/resizing/deletion/merging
	User mapping rules definition
	Automatic tie connection generation on new ports
	Automated correct-by-construction IP-XACT platform update at any level of hierarchy
	Component instance view update
Diff and Merge	List concurrent conflicts/changes
	Accept/Reject any change
	Conflict resolution wizard (choice selection, instance renaming…)
	On-the-fly checks to verify the validity of choices/conflict resolution
Import Memory Map Description	CSRSpec support
	SystemRDL support
	IP-XACT support
	Excel spreadsheets support
Generate HSI Outputs	RTL register bank (VHDL, Verilog, SystemVerilog)
	Customized C Header files
	UVM RAL files
	Documentation (Word, FrameMaker, HTML)
	SystemRDL description
	IP-XACT description
	Excel spreadsheet

SoC Connectivity

SoC Assembly with efficient handling of all aspects of system integration to make the design process easier, faster, and less risky, making the most of design teams’ productivity and expertise.

SoC Connectivity

Magillem Connectivity

Shorten, streamline, and de-risk the integration process through automation and built-in checkers to boost productivity, accelerating TTM and improving design quality.

Hardware / Software Interface

A single source of truth environment enabling effective collaborative development of the software and hardware interface, keeping all design teams in sync while mitigating design errors.

Hardware / Software Interface

Magillem Registers

Import memory map description in a single source of truth environment, ensuring synchronization between HW, SW, and documentation for automatic, consistent data generation.

Hardware / Software Interface

CSRCompiler

True cross-compiler engine producing all required views, to the entire team, for the development of the hardware/software interface with highest quality and performance.

Products

Coherent Interconnect

Non-Coherent Interconnect

Last-Level Cache

Packaging

SoC Connectivity

Hardware / Software Interface

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