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Ncore Cache Coherent Interconnect IP

High-Bandwidth, Low-Latency Network-on-Chip Interconnect

Ncore Cache Coherent Interconnect IP

Overview

Solving Multi-Core Design Challenges
With Safety Support

Arteris accelerates AI-driven silicon innovation with its expanded multi-die solution. Ncore™—our silicon-proven coherent Network-on-Chip IP—now extends full cache-coherency across chiplets, giving designers foundational technology for rapid, modular innovation.

Built on more than a decade of volume silicon, Ncore™ is highly configurable, power-efficient and works with any processor, including Arm® and RISC-V.

It is ISO 26262 ASIL D -ready and pairs with Magillem™ automation for IP integration software, so teams can scale modular architectures, simplify multi-die design and compress development schedules.

Ncore and FlexNoC together deliver unparalleled performance optimisation, scalability and system integration, enabling robust cache-coherence , efficient communication, and flexibility, leading to market differentiation and accelerated time-to-market. inside a die or across chiplets.

Advantages

The Only Multi-Processor, Multi-Die, Multi-Protocol, Highly Configurable Cache Coherent NoC

Empowers SoC developers to create high-performance coherent SoC

Scalable

Ncore provides a high-bandwidth, low-latency interconnect fabric for efficient communication between different components of an SoC and between multiple dies, offering scalable performance and power efficiency from small embedded systems to large multi-billion transistor and multi-die designs.

Configurable

Multi-protocol coherency gives choice and reuse for legacy and future IP support. CHI-E, CHI-B, and ACE coherent as well as ACE-Lite I/O coherent agent interfaces allow multiple initiator IPs to be connected to the same Ncore. Ncore also enables AXI non-coherent agents to act as I/O coherent agents.

Safe

ISO-certified by an external assessor to ensure Ncore readiness for use in ISO 26262 -compliant chips from ASIL B to ASIL D, enabled by the Ncore Safety and Reliability product option. Automated generation of Fault Modes Effects and Diagnostic Analysis (FMEDA) data for your Ncore configuration.

Ncore Key Features

Highly scalable system
True heterogeneous coherency with mixed AMBA CHI and AMBA ACE support
Full coherency for cached processors and I/O coherency for accelerators
Multi-die cache coherency over UCIe™ 1.1 via an AMBA CXS.B interface — up to four chiplets, and up to 4 × 64 GB/s links per die*
Configurable network and topologies
Mesh topology with physical tiling of repetitive blocks*
Functional safety with FMEDA generation and ASIL D certification*
Configurable snoop filters
I/O proxy cache and system memory cache
Low power consumption
Quality of Service (QoS)
Debug & trace/monitoring

* Denotes product option

Explore additional features of Ncore, download the datasheet.

Feature Spotlight

NoC Tiling — new feature with Ncore

NoC tiling with mesh topology for cache coherent CPUs. Up to 256 CPUs with 32-core cluster size.

Scale performance
Condense design time
Speed testing
Reduce design risk
Supports Arm and RISC-V architectures

Create modular, scalable designs, enabling faster integration, verification and optimization.

Ncore Product Benefits

Higher Frequencies, Lower Latencies

Use of multiple configurable snoop filters to accommodate different cache organization

Lower Power Consumption

Fewer off-chip main memory accesses resulting in lower power consumption

Smaller Die Area

Fewer wires using optimal NoC transport layer

Easy Configuration

Ncore adapts to each coherent agent’s behavior and characteristics

Faster Time to Market

Tiling accelerates physical design, implementation and timing closure

Flexible Topologies

Choose from crossbar, mesh and ad-hoc topologies

Safety

Automate FMEDA safety documentation, ISO26262 ASIL B to D certified

Automated Verification

Saving hundreds of hours of work over manual verification generation

Shorter Schedules

Fewer iteration loops

Ncore Product Options

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Option

Resilience: Safety

ISO 26262 ASIL D Certified
Multi-ASIL support

Option

Multi-Die

Multi-die cache coherent option for Ncore up to 4 dies
Homogeneous and heterogeneous architectures
Fully-connected or mesh topologies
Pre-integrated with 3rd-party UCIe 1.1 controller via AMBA CXS.B interface

Featured Solution

Arteris accelerates AI-driven silicon innovation with its expanded multi-die solution

Foundational technology for rapid chiplet-based design.

Flexible design scalability
Differentiated AI performance
Aligned with evolving industry standards

Built on silicon-proven NoC IP and Magillem™ automation to scale modular architectures, simplify multi-die projects, and compress development schedules.

Customer Testimonials

Trusted by innovative
 companies everywhere

We are happy to share that we are partnering with Arteris to use Ncore and FlexNoC IP in our next-generation product. The combination of performance and features made it a great choice for both our AI chips and our high-performance RISC-V CPUs. The Arteris team and IP solved our on-chip network problems so we can focus on building our next-generation AI and RISC-V CPU products.

We chose the Arteris Ncore cache coherent interconnect because of its unique proxy caches and their ability to underpin high-performance, low power, cache coherent clusters of our unique AI accelerators. And with our prior experience using FlexNoC and the FlexNoC FuSa Option for functional safety, we trust Arteris to be the highest performing and safest choice for ISO 26262-compliant NoC IP.

We are excited to partner with Arteris to accelerate the creation and delivery of an advanced communication SoC. Now, we can focus our resources where we bring the most value. Our company will leverage Arteris’ proven Ncore and FlexNoC technology and interconnect expertise for a combination that allows us to provide our customers with the best products in the shortest amount of time.

Arteris NoC technology enables wide on-chip bandwidth with fewer wires and lower latency than traditional bus and crossbar fabrics. This multiuse deal is expected to help us deliver these benefits more quickly to engineering teams throughout Freescale.

We have worked with Arteris NoC technology since 2010, and are excited that Arteris has brought its significant engineering prowess to help solve the problems of fault tolerant and reliable SoC design.

Resources

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Webinar

How to Achieve Efficient Communication and Data Sharing in Multi-Core SoC Designs

Datasheet

Ncore Multi-Die Option Datasheet

Video

Case Study

SCALINX Case Study

Presentation

Podcast

White Paper

Datasheet

Ncore® Cache Coherent Interconnect Datasheet

Cache coherent network-on-chip (NoC) interconnect IP Arm® AMBA® CHI and ACE interoperability; CCIX protocol support for multi-chip systems
ISO 26262-compliant functional safety mechanisms