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Arteris Wins Gold Stevie® Award for Most Innovative Tech Company of the Year
Arteris Wins Gold Stevie® Award for Most Innovative Tech Company of the Year, Plus Silver and Bronze Honors, in the 2025 International Business Awards®
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Arteris To Provide FlexGen Smart NoC IP In Next-Generation AMD AI Chiplet Designs
Arteris’ FlexGen smart NoC IP will be utilized by AMD in semiconductor designs to enable improved product performance and efficiency.
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Arteris Selected by Whalechip for Near-Memory Computing Chip
FlexNoC 5 network-on-chip interconnect IP from Arteris licensed by Whalechip, providing connectivity and enabling superior performance, area, and power for custom ASIC.
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Articles
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Semiconductor Engineering: A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution
With monolithic SoCs reaching their limits, chiplet-based architectures are key to building flexible, high-performance systems. Arteris’ multi-die solution combines silicon-proven NoC IP, cache coherency, and automation tools to streamline chiplet integration and accelerate time-to-market. Learn more in the article.
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RISC-V: Arteris’ Multi-Die Solution for the RISC-V Ecosystem
As AI, HPC, and automotive workloads push past the limits of monolithic SoCs, chiplet-based design offers a scalable and cost-efficient path forward. Arteris enables this shift with advanced NoC IP for coherent and non-coherent multi-die interconnects, UCIe-based die-to-die links, and
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Semiconductor Engineering: System Integration With Standards-Based Automation
As SoCs evolve into complex multi-die systems, standards-based automation is key. Learn how IP-XACT and Arteris’ Magillem tools enable consistent metadata, scalable IP reuse, and faster, error-free integration across teams and tools.
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EDN: Chiplet design basics for engineers
As AI and HPC workloads intensify, engineers are turning to chiplet-based architectures to overcome the limitations of traditional SoCs. This article explains the fundamentals of chiplet design, its advantages, and the tools enabling scalable, high-performance multi-die systems.
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EE Times: Smarter SoC Design for Agile Teams and Tight Deadlines
Advanced NoC automation helps lean SoC teams meet tight deadlines by reducing complexity, cutting design time, and improving power and performance efficiency.
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Design & Reuse: Enabling Chiplet Design Through Automation and Integration Solutions
Explore how chiplet-based designs overcome SoC limitations. Arteris’ multi-die solution enables connectivity across chiplets, supporting coherent and non-coherent traffic and intelligent dataflow management.
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Latest News
In the News
Catch the latest news headlines on Arteris’ advancements, industry-leading impact, and key developments.
SDxCentral: AMD licenses Arteris’ IP for development of next-generation chiplet interconnects – SDxCentral
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InsideHPC: AMD Licenses Arteris Network-on-Chip Interconnect IP | Inside HPC & AI News
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Semiconductor Engineering: For Chip Developers, HW/SW Co-Design Key To Data Center Efficiency
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SDxCentral: AMD licenses Arteris’ IP for development of next-generation chiplet interconnects – SDxCentral
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InsideHPC: AMD Licenses Arteris Network-on-Chip Interconnect IP | Inside HPC & AI News
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Semiconductor Engineering: For Chip Developers, HW/SW Co-Design Key To Data Center Efficiency
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