RISC-V: Arteris’ Multi-Die Solution for the RISC-V Ecosystem

The amount of compute used to train frontier AI models has been doubling roughly every five to six months, but ‘Moore’s Law’, the observation that the number of transistors on a silicon wafer doubles every 2 years, is slowing as reducing transistor sizes becomes increasingly challenging. Low yield of large chips, the need for increased flexibility, high development costs on the latest processes, overall chip size limits and the need for process technology specialization is driving the industry towards chiplet-based solutions. Furthermore, the lesser-known Dennard scaling, the observation that power reduces with decreased transistor size ceased to be true many years ago resulting in power consumption becoming an additional challenge to scaling chip size and frequency. As a result, processor designers have resorted to multi-core designs as a scalable approach to increased performance and recently to multi-die systems. In shared memory multi-core systems, hardware support for cache coherency is crucial to ensure data consistency between caches and memory and to maintain high performance.

RISC-V processors have quickly progressed from open-source microcontrollers to advanced multi-core cache coherent clusters that compare favorably with the most advanced in the industry. They are increasingly being deployed in HPC, servers, and AI applications, which push today’s semiconductor technology to the limit. Chiplets enable the scaling of performance beyond that of a single die, can improve yield, reduce cost, and facilitate an optimal process technology choice. Today, chiplets ship in relatively low volumes and mostly from large integrated companies creating fully in-house solutions, but market forecasts show explosive growth of 42-75% CAGR (Compound Annual Growth Rate) in the use of chiplets to 2030 and beyond.

Arteris customers using RISC-V processors have employed die-to-die interconnects for some time, typically with non-coherent interconnects (such as Arteris’ FlexNoC) that transfer data from chiplet to chiplet by packetizing a standard interface such as AMBA and sending it over a die-to-die interface such as UCIe or BoW (Bunch or Wires). But in June 2025, Arteris introduced coherent die-to-die connectivity which adds support for cache coherency across multiple chiplets. Coherency is far more complex than non-coherent protocols because it maintains consistency across caches, which requires protocol messages to be sent back and forth between agents in the system, and in a multi-die system, that means between agents in different chiplets. This contrasts with the much simpler A to B transfer of data in a non-coherent interconnect.

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