EE Times: Smarter SoC Design for Agile Teams and Tight Deadlines
- Rick Bye
- < 1 min read
Advanced NoC IP automation transforms SoC design by delivering expert-level topology, power efficiency, and performance, without requiring in-depth NoC expertise.
In the fast-paced semiconductor industry, rising demand for powerful, energy-efficient, and specialized electronics has driven strong growth in system-on-chip (SoC) development. This trend is expected to continue through 2030, particularly as edge AI design starts increase. Among the innovations shaping this space, edge AI has made significant strides in recent years, offering cost-effective solutions across an expanding range of applications. Its rapid evolution is enabling greater functionality across diverse market segments, with continued growth anticipated. SoCs are central to this progress, integrating multiple functions onto a single chip to enable faster data processing and decision-making without relying on cloud-based systems. The technology serves as the backbone of a wide range of applications across various markets, including industrial automation, automotive, networking, computing, consumer electronics, and space, as shown in Figure 1.
The SoC Design Bottleneck
SoC designs often comprise hundreds of IP blocks and tens of billions of transistors. Integrating these elements is a formidable task, especially for lean teams with limited resources.
Only a handful of companies can afford large in-house SoC design teams. Most rely on third-party design service providers. Even those with internal capabilities often split their resources into smaller, agile teams working on multiple projects to boost productivity and reduce time to market.
Traditional network-on-chip (NoC) technologies, which interconnect these IP blocks, often require specialized knowledge that many design teams lack. This expertise gap poses a significant hurdle, particularly for smaller, agile teams aiming to deliver high-performance SoCs within tight budgets and timelines.
