Arm and Arteris: Connecting the Future of Computing
Simplifying connectivity everywhere technology matters for mobility, communications, and intelligent IoT, driving the future of semiconductors with plug-and-play network-on-chip connectivity scalable from heterogeneous to mesh architectures.
Overview
Overview
Arm’s technology DNA centers on power-efficient computing, and we find it today everywhere technology matters. Arm compute platforms are the most power-efficient available and push the thresholds of performance to enable the next generation of intelligent, AI-capable, visually immersive, and more autonomous experiences on everything from the tiniest sensors to the smartphone to the automobile and the data center.
Arteris plays a crucial role in the Arm ecosystem, providing the tools and expertise needed to bring sophisticated Arm-based designs to life, and is strategically positioned to connect semiconductor IP building blocks in Arm-based designs, particularly in automotive mobility, mobile applications, and the Internet of Things (IoT), addressing the escalating demand for more intelligent, specialized devices. Arteris complements Arm’s architecture, renowned for its energy efficiency and performance, by offering advanced network-on-chip (NoC) and system-on-chip (SoCs) integration automation solutions that facilitate the seamless integration of Arm cores with other IP blocks, optimizing the design and functionality of complex systems on chips and systems of chiplets.
Arteris’ designed its configurable and scalable NoC solutions to streamline the integration process, allowing designers to focus on innovation and differentiation without being hindered by the underlying complexities of chip architecture. Arm and Arteris look back on almost two decades of collaboration, jointly ensuring that Arm-based designs are feasible and optimized for performance and energy efficiency. This collaborative approach helps accelerate the design-to-market process, minimize project risks, and ultimately enables the success of our mutual customers.
With over two decades of experience in NoC technology, Arteris empowers designers to exceed the growing expectations for Arm-based mobility, mobile, and IoT devices, driving the next wave of innovation in the semiconductor industry.
Advantages
Advantages
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Pre-Validation
Arteris' network-on-chip (NoC) technology and Arm's Automotive Enhanced (AE) Armv9 products have been pre-validated in emulation as part of our collaboration to ensure interoperability.
Expertise in Connectivity
With over 20 years of experience, Arteris simplifies the complexities of inter-chip and intra-chip connectivity, enabling designers to focus on core innovation while accelerating the design-to-market process.
Scalability
Create highly scalable ring, mesh, and heterogenous topologies and edit generated topologies - in contrast to black box compiler and mesh-only approaches - to optimize each network router.
In March 2024, Arteris delivered on its previously announced collaboration with Arm to speed up automotive electronics innovation with an emulation-based validation system for Armv9 and CHI-E-based designs to speed up innovation in automotive electronics for autonomous driving, advanced driver-assistance systems (ADAS), cockpit and infotainment, vision, radar and lidar, body and chassis control, zonal controllers and other automotive applications. Arteris aligned its roadmap with Arm to enable designers to get to market faster with an optimized and pre-validated high-bandwidth, low-latency Ncore cache coherent interconnect IP for Arm’s Automotive Enhanced (AE) compute portfolio. The partnership helps customers realize SoCs with high performance and power efficiency for safety-critical tasks while reducing project schedules and costs. It offers mutual customers a greater choice of safe, integrated, and optimized automotive solutions to enable faster time to market via seamless integration and optimized flows with the highest quality of results, enabling ISO 26262 systems with the highest automotive safety integrity levels (ASIL).
Introducing the latest release
of Ncore Cache Coherent NoC IP
Ncore is the only scalable, highly configurable, ISO 26262 certified cache coherent NoC for modern SoC designs.
- Any Processor
- Multiple Protocols
- Flexible Configuration
Maximize engineering productivity and accelerate time-to-market, saving 50+ person years over a DIY project.
Products
Products
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Customers
Trusted by innovative companies everywhere



- Accelerate Time To Market With a First-Time Right Process
- Arteris FlexNoC 5 – Industry’s First Physically Aware Network-on-Chip IP
- How to Achieve Efficient Communication and Data Sharing in Multi-Core SoC Designs
- Revolutionizing SoC Performance with Network-on-Chip Technology
- Three Perspectives on System Design Challenges
- Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design
- Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness
- FlexGen Product Tour
- Cache Coherency in Heterogeneous Systems
- Integration Challenges for RISC-V Designs
- Promises and Pitfalls of SoC Restructuring
- Scaling Performance in AI Systems
- Architecting the Future of Deep Learning Presentation
- Arm & Arteris AI and ISO 26262 Presentation
- Arm TechCon: Implementing ISO 26262 Compliant AI Systems-on-Chip with Arm and Arteris
- Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)
- Building Better IP with RTL Architect NoC IP Physical Exploration
- Challenges Adopting Fault Injection to Support Safety Analysis in Complex SoCs
- Efficient Scaling of AI Accelerators Using NoC Tiling
- FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)
- Fundamentals of ISO 26262 Part 11 for Semiconductors
- Implementing Low-Power AI SoCs Using NoC Interconnect Technology
- Implementing Machine Learning & Neural Network Chip Architectures
- Is the Missing Safety Ingredient in Automotive AI Traceability?
- ISO 26262 System-on-Chip (SoC) Safety Analysis for ADAS and AV
- ISO 26262: FMEA before FMEDA
- ISO 26262: What to Expect From Your Chip or IP Provider
- Lessons Learned Integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip
- Routing Congestion: The Growing Cost of Wires
- Safety Considerations for Network-on-Chip (NoC) Development
- The Role of Networks-on-Chips Enabling AI/ML Silicon and Systems
- Tiled Approach to System Scaling
- Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP
- EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling
- Electronic Design: All About NoCs
- SemiWiki: The Impact of Arteris on Automotive and Beyond with Frank Schirrmeister
- SemiWiki: A Broad View of Design Architectures and the Role of the NoC with Arteris’ Michal Siwinski
- EE Journal: The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster
- SemiWiki: The Impact of Using a Physically Aware NoC with Charlie Janac
- Making SoC Integration Simple – Achieve Higher Productivity and Quality
- A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow
- A Design Flow for Critical Embedded Systems
- A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis
- A SystemC Extension for Enabling Tighter Integration of IP-XACT Platforms with Virtual Prototypes
- AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases
- Application Driven Network-on Chip Architecture Exploration & Refinement for a Complex SoC
- Building a Portable Stimulus Flow Based on Magillem IP-XACT Packaging
- CodaCache: Helping to Break the Memory Wall
- Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product
- Generation of UVM Compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS
- How to Efficiently Achieve ASIL-D Compliance Using NoC Technology
- HW / SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures
- Optimizing Enterprise-Class SSD Host Controller Design with Arteris FlexNoC Network-On-Chip Interconnect IP
- Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding
- Re-Architecting SoCs for the AI Era
- Routing Congestion: The Growing Cost of Wires
- Scalability – A Looming Problem in Safety Analysis
- Security in Artificial Intelligence
- Using Machine Learning for Characterizations of NoC Components
- Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP
- Using Virtual Prototypes to Improve the Traceability of Critical Embedded Systems Flow
- Boost SoC Efficiency and Speed with FlexGen Smart NoC IP Automation White Paper
- Making Cache Coherent SoC Design Easier with Ncore
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