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Multi-Die Designs

Upgrade your data transport from Networks-on-Chips (NoCs) to Super-NoCs distributed across multiple chiplets

Multi-Die Designs

Overview

The insatiable drive toward higher performance and integration for semiconductor devices is propelling adoption of multi-die systems and chiplet-based designs—pushing Moore’s Law into the “More-than-Moore” era. Traditional monolithic chips can no longer satisfy the escalating demands of today’s complex, high-performance computing and AI workloads.

Arteris accelerates that AI-driven silicon innovation with its expanded multi-die solution. Built on silicon-proven NoC technology and Magillem™ automation, the platform delivers flexible design scalability, differentiated AI performance, and alignment with evolving industry standards.

Working with industry standards such as Arm AMBA, and with ecosystem partners that supply die-to-die PHYs—whether Universal Chiplet Interconnect Express™ (UCIe), Bunch of Wires (BoW) or proprietary links—Arteris NoC IP ensures seamless, low-latency data flow between chiplets so developers can hit aggressive performance, power and time-to-market goals despite the growing complexity of multi-die designs.

Advantages

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Interoperability

Connect to industry-leading die-to-die PHY connections using their digital controllers using standard interfaces like Arm AMBA protocols.

Bandwidth

Increase on-chip and off-chip bandwidth with HBM2 and multichannel memory support, multicast/broadcast writes, VC-Link™ Virtual Channels, and source-synchronous communications.

Low Power

Fewer wires and fewer gates consume less power, breaking communication paths into smaller segments allows to power only active segments, and simple internal protocol allows aggressive clock gating.

Multi-Die Use-Cases

Homogeneous Scale-Out

Demand for larger, scalable systems is driving the requirement for homogeneous solutions which enable a single chiplet design to be re-used multiple times to scale up to a larger system. A homogeneous chiplet solution may be selected because the design is too large for a reticle (858mm2) or yield issues would make a single die solution prohibitively expensive compared with multiple smaller dies with improved yield.

Heterogeneous Disaggregation

Heterogeneous disaggregation is a chiplet solution where the individual dies differ. The design may be too large for a single die, either due to reticle limits or yield (just as with heterogenous solutions) or multiple dies could facilitate the most appropriate semiconductor process for the application. For example, SRAM scaling has slowed since the 7nm node and SRAM in 3nm is no smaller than 5nm. If a die contains large amounts of SRAM it may be optimal to implement the SRAM on a lower cost, more mature process with higher yield. Likewise, specialist I/O (eg, high voltage) or RF may drive the solution towards a separate I/O chiplet.

Standards

From a system design perspective, choosing the proper NoC protocol for the die-to-die data transport is critical to meeting performance, latency, and power requirements. Providers of the physical connections typically deliver PHYs and Controllers, including Link Layers that carry the raw Flow Control Units (FLITs) from die to die.

Arteris already works with partners like Synopsys, Cadence, Alphawave, Blue Cheetah Analog, Innosilicon, and others to align on NoC to Controller/PHY interfaces. In addition, Arteris actively participates in the related standardization efforts. Specifically, Arteris actively engages in the following standardization efforts:

Products

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Coherent Interconnect

Ncore Cache Coherent Interconnect IP

Efficient coherent NoC interconnect that addresses key challenges in multi-core ASIC designs ensuring reliability, ISO26262 support, and optimized performance.

Non-Coherent Interconnect IP

FlexGen Smart Interconnect IP

Smart NoC IP automates the creation of high-performance NoC designs for 10x productivity boost, up to 30% wirelength reduction lowering latency and power consumption.

Non-Coherent Interconnect IP

FlexNoC Interconnect IP

Physically aware NoC with ISO26262 support option delivering up to 5X shorter turn-around-time on timing closure versus manual physical iterations.

Last-Level Cache

CodaCache Last-Level Cache IP

A last-level cache IP that solves key SoC challenges like performance, data access, timing closure, and layout congestion with a configurable caching solution.

SoC Connectivity

Magillem Connectivity

Shorten, streamline, and de-risk the integration process through automation and built-in checkers to boost productivity, accelerating TTM and improving design quality.

Hardware / Software Interface

Magillem Registers

Import memory map description in a single source of truth environment, ensuring synchronization between HW, SW, and documentation for automatic, consistent data generation.

Packaging

Magillem Packaging

A fully automated solution to import legacy RTL and create correct by-construction IP-XACT description, map the physical ports into bus interface, and capture the memory map.

Customer Testimonials

Trusted by innovative
companies everywhere

As Al pushes the limits of performance and power efficiency, monolithic SoCs with chiplet capabilities have become essential in delivering the integration and scalability that traditional SoC designs can't match. Arteris technology plays a key role in realizing this vision by providing the underlying connectivity in our 5th generation R-Car automotive silicon and driving the new era of automotive innovation.

AMD is driving innovations that scale AI from cloud to client by continually developing leadership computing technologies and best-in-class IP. Integrating Arteris’ FlexGen NoC IP technology into a range of AMD chiplets, we can automate interconnect configuration and enable seamless connectivity among SoC components while strengthening the best end-to-end AI compute portfolio in the industry.

Rebellions have utilized Arteris interconnect IP and SoC integration software in select products to support performance optimization and efficient integration across our Al accelerator development efforts. Arteris FlexNoC interconnect IP and Magillem software have contributed to our design workflows, aligning with our focus on modular and scalable Al system architectures.

We continue to leverage Arteris' network-on-chip IP products in our designs as we drive the next wave of advancements in Al computing. Arteris is a proven technology partner - their FlexNoC IP provides superior performance for our next-generation Al compute.

Arteris' technology allows us to achieve the performance and area targets we need for our MOSAICS-LP platform. The proven capabilities of Arteris' network-on-chip IP ensure efficient scaling of our solutions while streamlining our design process.

Resources

Webinar

Datasheet

Ncore Multi-Die Option Datasheet

Video

Presentation

Podcast

Solution Brief

Accelerate AI-Driven Silicon Innovation with Arteris Multi-Die Solution

White Paper

What's New

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Multi-Die Designs