Multi-Die Archives

Semiconductor Engineering: A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution

With monolithic SoCs reaching their limits, chiplet-based architectures are key to building flexible, high-performance systems. Arteris’ multi-die solution combines silicon-proven NoC IP, cache coherency, and automation tools to streamline chiplet integration and accelerate time-to-market. Learn more in the article.

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RISC-V: Arteris’ Multi-Die Solution for the RISC-V Ecosystem

As AI, HPC, and automotive workloads push past the limits of monolithic SoCs, chiplet-based design offers a scalable and cost-efficient path forward. Arteris enables this shift with advanced NoC IP for coherent and non-coherent multi-die interconnects, UCIe-based die-to-die links, and

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EDN: Chiplet design basics for engineers

As AI and HPC workloads intensify, engineers are turning to chiplet-based architectures to overcome the limitations of traditional SoCs. This article explains the fundamentals of chiplet design, its advantages, and the tools enabling scalable, high-performance multi-die systems.

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Design & Reuse: Enabling Chiplet Design Through Automation and Integration Solutions

Explore how chiplet-based designs overcome SoC limitations. Arteris’ multi-die solution enables connectivity across chiplets, supporting coherent and non-coherent traffic and intelligent dataflow management.

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EDN: Chiplet basics: Separating hype from reality

Planning chiplet-based designs is underway. Yet, uncertainty continues to swirl around chiplet architecture and ready-to-use technologies. New innovations are on the horizon.

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