RISC-V and Arteris: Shaping the Future of Chip Design
Unleashing innovation, simplifying connectivity, and driving the new era of specialized semiconductors with plug-and-play network-on-chip connectivity
Overview
Overview
RISC-V is revolutionizing the semiconductor world with its promise of freedom to innovate and enable specialization, fueling the golden age of semiconductors. The world craves smarter, more specialized devices. RISC-V is rising to meet this demand, especially in artificial intelligence and machine learning for automotive, enterprise computing, consumer, communications, and industrial applications, allowing developers to tailor-make solutions to meet specific needs.
But innovation doesn’t exist in a vacuum. As designers innovate with RISC-V, they need tools and partners to bring their visions to life. Arteris is a central player in the chip design ecosystem, providing plug-and-play solutions to connect 100s of re-used and custom-design blocks through its network-on-chip (NoC) technology. It enables seamless integration of RISC-V cores with other IP blocks, ensuring that devices not only work but work efficiently. Unifying various NoC protocols allows developers to focus on their unique differentiation, leaving the NoC complexity to Arteris’ NoC technology with 20+ years of experience. While designers focus on innovating the RISC-V cores, Arteris handles the complexities of inter-chip and intra-chip connectivity, de-risking projects and speeding up the design-to-market process.
In addition, Arteris works closely with IP partners, ensuring a smooth interaction between different components on a chip. Their expertise means they can co-optimize design aspects, ensuring that computing and transport systems work harmoniously. The RISC-V trend, powered by partners like Arteris, is set to transform the semiconductor landscape in a world hungry for more innovative, faster devices.
Advantages
Advantages
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Seamless Integration
Arteris' network-on-chip technology ensures effortless integration of RISC-V cores with other IP blocks, making devices functional and efficient.
Expertise in Connectivity
With over 20 years of experience, Arteris simplifies the complexities of inter-chip and intra-chip connectivity, enabling designers to focus on core innovation while accelerating the design-to-market process.
Scalability
Create highly scalable Ring, Mesh, and Torus topologies and edit generated topologies - in contrast to black box compiler approaches - to optimize each individual network router.
Andes Technology is a founding and premier member of RISC-V International and a leading supplier of high-performance/low-power RISC-V processor IP. Andes Technology and Arteris partner to advance innovation for RISC-V based SoC designs for AI, 5G, networking, mobile, storage, AIoT and space applications. The Andes QiLai RISC-V platform is a development board with a QiLai SoC featuring the Andes’ RISC-V processor IPs along with Arteris FlexNoC interconnect IP used for on-chip connectivity.
The Damo Wujian Alliance, spearheaded by Damo Academy (an affiliate of Alibaba Group), is an ecosystem alliance driving the adoption and development of the RISC-V instruction-set architecture. The coalition focuses on high-performance System-on-Chip (SoC) designs, particularly in edge AI computing. As part of the alliance, Arteris plays a pivotal role by enabling the integration of Damo Academy’s / T-Head’s Xuantie RISC-V processor IP cores with its Ncore cache coherent network-on-chip (NoC) system IP, resulting in efficient data transport architectures within cores and between chips, enabling cutting-edge applications in AI, machine learning, and more.
MIPS is accelerating compute density in the automotive, cloud and embedded markets. Giving customers the freedom to build unique products for specific workloads, MIPS’ industry-leading cores are configurable, efficient, and easy to implement. To extend those benefits, MIPS and Arteris provide a pre-verified reference platform aimed at shortening development cycles and reducing risk for RISC-V-based chip designs.
Semidynamics is a provider of fully customizable RISC-V processor IP and specializes in high bandwidth, high-performance cores with Vector Units, Tensor Units and Gazzillion, and targeted at machine learning and AI applications. Our collaboration enhances the flexibility and highly configurable interoperability of processor IP with system IP, aiming to deliver Integrated and optimized solutions with focus on accelerating artificial intelligence, machine learning and high-performance computing (HPC) applications.
SiFive and Arteris have partnered to accelerate the development of AI and Machine Learning compute from edge AI SoCs for consumer electronics and industrial applications to AI workloads for datacenters, vehicles, and embedded systems. The partnership combines SiFive’s multi-core RISC-V processor IP and Arteris’ Ncore cache coherent interconnect IP, providing high performance and power efficiency with reduced project schedules and integration costs. The collaboration has led to the development of emulation-ready reference designs with the X280 and P870-D processors, as an example of ways in which mutual customers can accelerate development and get their products to market faster.
Synopsys is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, IP and services used in semiconductor design and manufacturing. Synopsys’ comprehensive, integrated portfolio of advanced technologies helps customers innovate from silicon to software so they can bring amazing new products to life. Our partnership focuses on connections between network-on-chip development and Synopsys architecture analysis and digital implementation.
Introducing the latest release
of Ncore Cache Coherent NoC IP
Ncore is the only scalable, highly configurable, ISO 26262 certified cache coherent NoC for modern SoC designs.
- Any Processor
- Multiple Protocols
- Flexible Configuration
Maximize engineering productivity and accelerate time-to-market, saving 50+ person years over a DIY project.
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