Overview
Enabling SoC Developers
to Create Efficient NoCs
The world’s #1 on-chip fabric is used by the world’s top semiconductor design teams as the backbone on-chip communications for chips targeting the fastest growing markets.
Arteris FlexWay™ 5 network-on-chip (NoC) IP is particularly well suited to cost-efficient, low-power Internet-of-Things (IoT) edge devices and microcontrollers (MCUs).
Advantages
A Complete Network-On-Chip Product
Everything design teams need to create the world’s best SoCs, faster
Flexible Topologies
FlexWay is generated from simple elementary components which are combined by a powerful set of algorithms and an intuitive GUI, making it possible to build the optimal topology for your embedded application.
Small to Medium SoCs
FlexWay supports simple to medium-complexity designs and easily scales efficiently between the two, containing only the optimum configuration required.
Huge Bandwidth
FlexWay is uncompromising in how it drives performant on-chip dataflow despite it’s power efficient design.
Features
FlexWay Key Features
- Multi-clock/power/voltage domains and power management with unit-level clock gating
- Multi-protocol support including AMBA 5 with QoS bandwidth regulator and limiter
- Integrated SystemC simulation & UVM verification support
- Import and Export to Magillem tools
- AMBA 5 support of DVM 8.1 (Device Virtual Messaging)
- On-chip performance monitoring and debug
- Debug and trace with ATB 128b and timestamps
Explore additional features of FlexWay, download the datasheet.
Efficient Transport of Data Through the SoC
Arteris CodaCache® last-level cache:
- Ideal for NoC applications with data re-use
- Improves overall SoC latency and power
Efficient Transport of Data Through the SoC

NoC Integration Automated Flow
Automated flow to leverage SoC connectivity information:
- Improved productivity with reduced process
- Better quality with early errors detections thanks to the checkers
NoC Integration Automated Flow

Benefits
FlexWay Product Benefits
Easy Configuration
Through the intuitive FlexWay UI
Automated Verification
Saving hundreds of hours of work versus manual verification test benches
Lower Power Consumption
Advanced power management through clock gating, DVFS and GALS
Smaller Die Area
Fewer wires using optimal NoC transport layer
Product Comparison
Product Comparison
Product Comparison Table
Category | Features | FlexWay | FlexNoC | FlexGen |
---|---|---|---|---|
Target Audience and Scale | Smaller-scale MCU SoCs | |||
Small-medium scale SoCs | ||||
Large scale SoCs | ||||
Instances Per Design | Single NoC instance | |||
Multiple NoC instances | ||||
Network Interface Units (NIUs) | Up to 50 NIUs | |||
Up to 200 NIUs | ||||
Up to 1000 NIUs | with XL option | with XL option | ||
Compatibility | AXI, AHB, APB, OCP, PIF, AMBA5 | |||
ACE-Lite | ||||
Smart NoC Automation | Topology generation with minimum wire length | |||
Scripting-driven regular topology creation | ||||
Incremental design capability | ||||
Physical Awareness | Automatic timing closure assistance | |||
Floorplan visualization | ||||
Advanced Scalability | NIU tiling | with XL option | with XL option | |
Mesh topology editor | with XL option | with XL option | ||
Write broadcast stations | with XL option | with XL option | ||
Virtual channel links | with XL option | with XL option | ||
Source synchronous asynchronous bridges | with XL option | with XL option | ||
Up to 1024 bits data bus | with XL option | with XL option | ||
512 pending transaction support | with XL option | with XL option | ||
Optimizations | Optimization for performance, area and wire length | |||
Advanced Quality of Service (QoS) | ||||
Power management and security | ||||
Address and data protection schemes | ||||
Advanced in-circuit debug features | ||||
Multi-cycle SRAM support | ||||
Floorplan visualization | ||||
Add-on Options | Memory Re-order Buffer option | |||
Reliability option | ||||
Safety (up to ISO 26262 ASIL D) option | ||||
Advanced Scalability (XL) option | ||||
Markets | Automotive, Communications, Consumer Electronics, Enterprise Computing and Industrial Markets |
Option
FlexWay Product Option
Seamlessly integrated extensions to the base FlexWay feature set
- ISO 26262 Functional Safety (FuSa)
- Multi-ASIL support
- Interconnect-wide ECC support




Resources
Resources
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- Architecting the Future of Deep Learning Presentation
- Arm & Arteris AI and ISO 26262 Presentation
- Arm TechCon: Implementing ISO 26262 Compliant AI Systems-on-Chip with Arm and Arteris
- Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)
- Building Better IP with RTL Architect NoC IP Physical Exploration
- Challenges Adopting Fault Injection to Support Safety Analysis in Complex SoCs
- Efficient Scaling of AI Accelerators Using NoC Tiling
- FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)
- Fundamentals of ISO 26262 Part 11 for Semiconductors
- Implementing Low-Power AI SoCs Using NoC Interconnect Technology
- Implementing Machine Learning & Neural Network Chip Architectures
- Is the Missing Safety Ingredient in Automotive AI Traceability?
- ISO 26262 System-on-Chip (SoC) Safety Analysis for ADAS and AV
- ISO 26262: FMEA before FMEDA
- ISO 26262: What to Expect From Your Chip or IP Provider
- Lessons Learned Integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip
- Routing Congestion: The Growing Cost of Wires
- Safety Considerations for Network-on-Chip (NoC) Development
- The Role of Networks-on-Chips Enabling AI/ML Silicon and Systems
- Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP
- Application Driven Network-on Chip Architecture Exploration & Refinement for a Complex SoC
- Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product
- How to Efficiently Achieve ASIL-D Compliance Using NoC Technology
- Optimizing Enterprise-Class SSD Host Controller Design with Arteris FlexNoC Network-On-Chip Interconnect IP
- Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding
- Re-Architecting SoCs for the AI Era
- Routing Congestion: The Growing Cost of Wires
- Scalability – A Looming Problem in Safety Analysis
- Security in Artificial Intelligence
- Using Machine Learning for Characterizations of NoC Components
- Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP
- Using Virtual Prototypes to Improve the Traceability of Critical Embedded Systems Flow
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