Design & Reuse: Enabling Chiplet Design Through Automation and Integration Solutions

Chiplet-based, multi-die systems are gaining traction as a compelling alternative to monolithic system-on-chip (SoC) designs. These architectures are enabled by die-to-die (D2D) connectivity advances and driven by the need to overcome reticle limitations and improve yield. Designers can integrate homogeneous or heterogeneous functions, with each die implemented using the most appropriate process node for performance, power, and area. This disaggregation introduces new design challenges, including system-level integration, handling coherent and non-coherent traffic, and managing register address mapping across multiple dies.

There are several practical reasons for this momentum. One of the most important is that it allows engineers to create systems that exceed the physical limitations of a single monolithic die, which is 858 mm2 at the time of writing. By distributing functionality across multiple smaller dies, these architectures enable the implementation of larger, more capable designs within a single package.

Smaller individual dies also tend to yield better during manufacturing, which can lead to significant cost savings at scale. Beyond economics, chiplets introduce new flexibility into design strategy. Processing elements such as CPUs, GPUs, NPUs, and other accelerators can be selected for their strengths and combined with in-package memory or interface controllers to meet specific performance goals.

These systems may be composed of identical processing units that scale performance through replication or a mix of different elements that each serve a specialized role. For example, multi-die SoC designs can incorporate high-speed logic in 3 nm, dense SRAM in 7 nm, and high-voltage I/O on a 28 nm process. Teams can reuse existing components and more easily build product variations by reconfiguring the chiplet assembly rather than redesigning the entire system.