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Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.

Video

Accelerating IP Reuse

Semiconductors now rely on up to 1,000 third-party IPs in complex SoCs, requiring seamless integration. Insaf Meliane of Arteris discusses with Semiconductor Engineering how the latest IP-XACT version simplifies automation, abstraction, and system integration.

Video

Cache Coherency in Heterogeneous Systems

Why maintaining flexibility in coherency is essential in heterogeneous designs. A video discussion with Semiconductor Engineering’s Ed Sperling.

Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.

Video

Promises and Pitfalls of SoC Restructuring

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.

Video

Scaling Performance in AI Systems

AI designs face increasing challenges in balancing power, performance, and data throughput. Andy Nightingale from Arteris discusses how network-on-chip technology can help alleviate these bottlenecks and accelerate chip time-to-market.

White Paper

A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow

This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation.

White Paper

Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product

Written by an ISO 26262 working group member who contributed to the new ISO 26262:2018 Part 11, this paper dispels myths about ISO 26262 certification and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.

White Paper

How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

A closer look at ASIL-D compliance options for on-chip interconnects and NoCs, including redundancy, path diversity and error correction codes (ECC) is required to fully optimize an on-chip network to meet rapidly evolving technology and customer demands.

White Paper

Mobileye Case Study: Using Arteris for ADAS

In this 4-page paper, created with the participation of Mobileye, you will learn how the world’s #1 vision-based automotive ADAS company uses Arteris FlexNoC interconnect IP to address demanding high bandwidth and low-latency requirements.

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Resources Search

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Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

Accelerating IP Reuse

Cache Coherency in Heterogeneous Systems

Integration Challenges for RISC-V Designs

Promises and Pitfalls of SoC Restructuring

Scaling Performance in AI Systems

A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow

Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product

How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

Mobileye Case Study: Using Arteris for ADAS

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