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Semiconductor Engineering: A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution
With monolithic SoCs reaching their limits, chiplet-based architectures are key to building flexible, high-performance systems. Arteris’ multi-die solution combines silicon-proven NoC IP, cache coherency, and automation tools to streamline chiplet integration and accelerate time-to-market. Learn more in the article.
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RISC-V: Arteris’ Multi-Die Solution for the RISC-V Ecosystem
As AI, HPC, and automotive workloads push past the limits of monolithic SoCs, chiplet-based design offers a scalable and cost-efficient path forward. Arteris enables this shift with advanced NoC IP for coherent and non-coherent multi-die interconnects, UCIe-based die-to-die links, and
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EDN: Chiplet design basics for engineers
As AI and HPC workloads intensify, engineers are turning to chiplet-based architectures to overcome the limitations of traditional SoCs. This article explains the fundamentals of chiplet design, its advantages, and the tools enabling scalable, high-performance multi-die systems.
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EE Times: Smarter SoC Design for Agile Teams and Tight Deadlines
Advanced NoC automation helps lean SoC teams meet tight deadlines by reducing complexity, cutting design time, and improving power and performance efficiency.
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Electronic Design: Breaking Barriers in SoC Design with Smart NoC Automation
As SoCs grow in complexity, manual NoC generation is no longer practical. Discover how how automated NoC generation streamlines interconnect development to improve efficiency, scalability, and performance in advanced semiconductor designs.
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Semiconductor Engineering: Data Movement Is the Energy Bottleneck of Today’s SoCs
In today’s AI-focused semiconductor landscape, raw compute performance alone no longer defines the effectiveness of a system-on-chip (SoC). Learn more about how the right interconnect ensures that design teams are well-equipped to meet workload demands while achieving the performance and
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