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Podcast

SemiWiki: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale

Dan talks with Andy Nightingale from Arteris about new tiling capabilities and extended mesh topology support for network-on-chip IP products. They explore how these features address AI-driven chip design challenges.
FlexGen Smart NoC IP from Arteris Revolutionizes Complex SoC Designs -new
Video

FlexGen Smart NoC IP from Arteris Revolutionizes Complex SoC Designs

FlexGen smart NoC IP enables automated NoC design with reduced manual effort, shorter iteration cycles, and expert-level quality of results. SoC design teams can realize faster time-to-market, optimized power plus performance, reduced wire length, and improved overall design economics with FlexGen.
Guillaume accelerating timing closure
Video

Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness

Learn how to accelerate timing closure for Networks-on-Chip (NoCs) using physical awareness. Discover a flow and methodology to optimize NoC development and avoid timing surprises.
Chiplets: Opportunities and Challenges
Video

Chiplets: Opportunities and Challenges

Explore the challenges of chiplet interoperability and ecosystem collaboration and how leading companies are navigating this shift.
NoC-Centric System Performance for the Chiplet-Era with Platform Architect
Video

NoC-Centric System Performance for the Chiplet-Era with Platform Architect

Explore how Arteris NoC IPs and Platform Architect enhance system-level analysis for SoC designs in the chiplet era at the Synopsys Virtual Prototyping Day 2025.
Optimizing Data Transport Architectures in RISC–V SoCs for AIML Applications
Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.
Smart NoC IP - Revolutionizing SoC Design
Video

Revolutionizing Semiconductor Design with Smart NoC IP

Learn how FlexGen Smart NoC IP can optimize and advance your semiconductor design processes. Designed for automotive, data centers, and industrial electronics applications, it enables faster time-to-market and/or multiple design explorations for the most complex systems.
Podcast

EE Times: Automating NoC Design Masters SoC Complexity

In this podcast, Sally Ward-Foxton and Michal Siwinski discuss how FlexGen, smart NoC IP, is revolutionizing NoC design through automation and why this is crucial for today’s chips. How it addresses the growing demands of AI, and what the future holds for NoC technology.
FlexGen Product Tour image
Video

FlexGen Product Tour

Watch an overview showing how FlexGen smart NoC IP generates a network-on-chip for your SoC in minutes. The RTL is correct-by-design, wire length optimized to meet all the specified performance requirements and floorplan constraints of your design.
SemiEngineering Whiteboard Integration Challenges For RISC-V Designs
Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.

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