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Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness

Learn how to accelerate timing closure for Networks-on-Chip (NoCs) using physical awareness. Discover a flow and methodology to optimize NoC development and avoid timing surprises.

Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.

Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.

Video

Promises and Pitfalls of SoC Restructuring

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.

Video

Scaling Performance in AI Systems

AI designs face increasing challenges in balancing power, performance, and data throughput. Andy Nightingale from Arteris discusses how network-on-chip technology can help alleviate these bottlenecks and accelerate chip time-to-market.

White Paper

Application Driven Network-on Chip Architecture Exploration & Refinement for a Complex SoC

Peer-reviewed technical journal article from Springer’s “Design Automation for Embedded Systems Journal.” Summarizes the various features a NoC is required to implement to be integrated in modern SoCs. Describes a top-down approach, based on the progressive refinement of the NoC description from its functional specification (Sect. 4) to its verification (Sect. 8).

White Paper

Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product

Written by an ISO 26262 working group member who contributed to the new ISO 26262:2018 Part 11, this paper dispels myths about ISO 26262 certification and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.

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SemiWiki: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale

Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness

Chiplets: Opportunities and Challenges

NoC-Centric System Performance for the Chiplet-Era with Platform Architect

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

Integration Challenges for RISC-V Designs

Promises and Pitfalls of SoC Restructuring

Scaling Performance in AI Systems

Application Driven Network-on Chip Architecture Exploration & Refinement for a Complex SoC

Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product

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