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Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design

Magillem Registers is a comprehensive register design and management technology that accurately automates the hardware/software interface (HSI) to quickly develop chips and chiplets ranging from IoT devices to complex AI datacenter multi-die SoCs.

Video

Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness

Learn how to accelerate timing closure for Networks-on-Chip (NoCs) using physical awareness. Discover a flow and methodology to optimize NoC development and avoid timing surprises.

Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.

Video

FlexGen Product Tour

Watch an overview showing how FlexGen smart NoC IP generates a network-on-chip for your SoC in minutes. The RTL is correct-by-design, wire length optimized to meet all the specified performance requirements and floorplan constraints of your design.

Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.

Video

Promises and Pitfalls of SoC Restructuring

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.

Video

Scaling Performance in AI Systems

AI designs face increasing challenges in balancing power, performance, and data throughput. Andy Nightingale from Arteris discusses how network-on-chip technology can help alleviate these bottlenecks and accelerate chip time-to-market.

White Paper

Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding

An oldie but a goodie: Explains power benefits of NoC technology by characterizing a multi-processor system-on-chip (MPSoC) for MPEG4, AVC/H.264 encoding. Explains NoC power model used to analyze power consumption and dissipation.

White Paper

Re-Architecting SoCs for the AI Era

This paper defines AI, describe its applications, the problems it presents, and how chip designers can address those problems through new and holistic approaches to SoC and network on chip (NoC) design.It also describes challenges implementing AI functionality in automotive SoCs with ISO 26262 functional safety requirements.

White Paper

Routing Congestion: The Growing Cost of Wires

The congestion of wires in the place and route (P&R) stage of chip design poses an increasingly significant challenge to creating low cost, high performance chip designs. This paper introduces packet based network-on-chip as a means of enabling configuration link widths, shows experimental results, and describes other benefits of packet-based interconnect networks.

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Resources Search

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Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design

Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

FlexGen Product Tour

Integration Challenges for RISC-V Designs

Promises and Pitfalls of SoC Restructuring

Scaling Performance in AI Systems

Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding

Re-Architecting SoCs for the AI Era

Routing Congestion: The Growing Cost of Wires

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