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AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases

This 12-page paper published in the peer-reviewed IEEE Design & Test journal explains how Universal Verification Methodology (UVM), initially developed for digital systems, can be extended to analog and mixed signal systems with the help if IP-XACT-based IP packaging and design flow automation.

White Paper

Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product

Written by an ISO 26262 working group member who contributed to the new ISO 26262:2018 Part 11, this paper dispels myths about ISO 26262 certification and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.

White Paper

How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

A closer look at ASIL-D compliance options for on-chip interconnects and NoCs, including redundancy, path diversity and error correction codes (ECC) is required to fully optimize an on-chip network to meet rapidly evolving technology and customer demands.

White Paper

Mobileye Case Study: Using Arteris for ADAS

In this 4-page paper, created with the participation of Mobileye, you will learn how the world’s #1 vision-based automotive ADAS company uses Arteris FlexNoC interconnect IP to address demanding high bandwidth and low-latency requirements.

White Paper

Scalability – A Looming Problem in Safety Analysis

Misbehavior in the electronics can lead to accidents, even fatalities. This paper describes how ISO 26262 standard and in particular the Failure Modes, Effects and Diagnostic Analysis (FMEDA) can be leveraged to address this real concern.

White Paper

Using Machine Learning for Characterizations of NoC Components

This Award Winning Paper was presented at Synopsys SNUG Silicon Valley 2019. You will learn about modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters. PPA (performance/power/area) estimates for these components are highly desirable during early design phases – long before NoC gate level netlist is synthesized.

Network-on-Chip (NoC)

White Paper

Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP

Presentation

Arm & Arteris AI and ISO 26262 Presentation

Arm & Arteris joint presentation from ICCAD China 2018 describes how new artificial (AI) and machine learning (ML) acceleration IP from Arm, like the Arm® NPU and Mali™ C71, can be implemented in ISO 26262-compliant automotive systems with the help of functional safety mechanisms in the Arteris FlexNoC and Ncore interconnects.

Presentation

Arm TechCon: Implementing ISO 26262 Compliant AI Systems-on-Chip with Arm and Arteris

Arm, Arteris, and Dream Chip Technologies joint presentation from Arm TechCon 2019 explains IP integration requirements for AI subsystems in ISO 26262-compliant chips. With an emphasis on techniques and safety mechanisms to enhance the diagnostic coverage of SoCs integrating an NPU and Safety Island. Topic areas include system design to comply with ISO 26262, system-level diagnostics, Network-on-Chip (NoC) safety mechanisms, subsystem isolation, and end-to-end error protection.

Presentation

Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)

Presented at IQPC Application of ISO 26262 2022 Conference, describes an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics at a level that scales with the size and complexity of an SoC and enables reuse for the creation of SoC platform derivative chips, which is common in our industry.

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AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases

Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product

How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

Mobileye Case Study: Using Arteris for ADAS

Scalability – A Looming Problem in Safety Analysis

Using Machine Learning for Characterizations of NoC Components

Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP

Arm & Arteris AI and ISO 26262 Presentation

Arm TechCon: Implementing ISO 26262 Compliant AI Systems-on-Chip with Arm and Arteris

Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)

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